1. Field of the Invention
This invention relates generally to radio signal processing, and more specifically to a multi-megabit-data-rate baseband signal processor within a microwave radio receiver adapted to the size and power drain requirements for use with battery-powered portable computers. The processor's capabilities include those necessary for dealing with adverse distortion from radio propagation.
2. Description of the Prior Art
There is considerable prior art on the technologies of the invention, but not within the difficult constraints defined. Relevant prior art for portions of the invention are found in the following fields:
1) In a spread spectrum radio system, receiving correlator and data processing circuit design for implementation at multimegabit data rates based on the use of analog delay lines working at baseband. PA1 2) diversity combining for primary and delayed propagation paths and including "RAKE" receivers for spread spectrum. PA1 3) differential amplitude detection to decrease sensitivity to signal amplitude uncertainty. PA1 4) matched filter demodulation with RC integrator. PA1 5) direct sequence spread spectrum signal design with imperfect or semi-optimum spreading codes for high ratios of transferred information relative to occupied radio bandwidth. PA1 6) selection of code patterns for minimum cross correlation while providing auto-correlation, e.g. "Barker" and "Gold" used in direct sequence spread spectrum. PA1 a) very small size and low battery drain circuits including passive components, and PA1 b) use of data rates sufficiently high to stress the speed limits of monolithic analog and digital integrated circuits, and PA1 c) application to time dispersive multipath distortion in the transmission medium (radio propagation in this case), and PA1 d) providing enhanced resistance to such time dispersion obtained from the combination of time and multiple antenna diversity, and PA1 e) staying within constraints requiring the highest workable ratio of data rate to bandwidth occupied. PA1 1) Filter-based delay line correlation with the analog sum of the taps to detect the correlation peak for a single combining pattern. PA1 2) Use of Barker pattern for spectrum spreading sequence, and use of the opposite polarity to obtain binary coding. PA1 3) Use of Barker pattern for spectrum spreading sequence and pulse compression in radar where the propagation path is free space and very long. PA1 4) Use of a diminished cross-correlation orthogonality for a set of symbols to increase the number of available auto-correlation patterns available for a given symbol length. PA1 5) Use of the average value of a correlator output as a reference for differential detection of the correlation peak for completely orthogonal (Barker) symbol formats. PA1 6) Design methods for flat delay lowpass filters using discrete components. PA1 7) Use of more than one binary patterned symbol commonly based on "Gold" codes to create multiple simultaneously usable symbol values for channelization with symbols of 31 chips or more. PA1 8) Use of more than one binary patterned symbol to create multiple one-at-a-time usable symbol values for increased information per symbol with symbols of 31 chips or more, and where orthogonality between symbols exists at only one time position of the symbol; and where the symbols become simultaneously usable only when the multiple signals have synchronized timing and equalized amplitude at the receiving point. PA1 9) Power conservation by selectively powering circuit functions only when signal is present based on carrier detection. PA1 10) Power conservation by selectively powering a digital circuit only when its function is needed. PA1 Symbol length: 7 chips/symbol PA1 Chipping rate: 35 Mchips/sec PA1 Propagation distance during one chip: 8.58 meters PA1 Data and delimiters: 1-of-6 chip patterns PA1 Synchronization: normal "Barker" pattern PA1 PHY level and fall-back signaling: normal/invert "Barker" PA1 Pattern squareness: 3/7 or 4/7 1's
Many prior art implementations have not considered the following simultaneous requirements:
Taken one-at-a-time, the below listed points are known prior art. The qualifiers given cannot be altered to either diminish or expand the scope without reconsidering whether or not they remain within prior art.
In direct sequence spread spectrum modulation, the processing gain at best reverses the loss from spreading. If the given bandwidth is fixed, so is the maximum chipping rate holding modulation method constant. There is then a choice on the use of code space.
Most prior art references are for a multi-channel telephone service with many channels operated simultaneously at a low fixed rate. The described signal processor is for a single channel operated at the highest feasible rate sequentially allotted to users for a much shorter time.
Parallel and Simultaneous Low Rate Channels
For some prior art pocket telephones, a 512 chip symbol has been selected with the possibility of using 128 different codes at the same time, each providing a 32 Kbits/sec telephone channel at one bit per symbol. The ratio of chips-to-bits for the composite signal is in the range from 4:1 to 10:1 depending on system details. This process requires that all of the channel signals be adjusted to be received with common timing and amplitude at a common receiver.
Each code represents one voice channel in which the signal-to-noise ratio of a particular bit stream gets the benefit of the 512:1 processing gain if it is done before there is a nonlinearity in the signal path. This simultaneous use produces a higher composite noise level than for one signal alone. The increased noise of simultaneous use balances off the advantage of the large processing gain when the number of simultaneous channels is maximized.
One Sequentially Used High Rate Channel
Suppose now a LAN data system occupies exactly the same frequency space, but chooses a symbol length of 7 chips from which 4 codes are used to get 2 bits of information. The chip-to-bit ratio is 3.5, slightly better than the parallel system above. In addition, the noise of 127 other simultaneous users is not a consideration because the channel is used sequentially.
The aggregate throughput of the parallel mode is 128 bits per 512 chips while the sequential mode is about 146 bits per 512 chips. For the second system to carry the same traffic, each user would use the channel 1/146th of the time at 128 times the rate of the 512 chip symbol with time left over.
The air interface of this invention uses a short, simple symbol and intensely uses the code space to maximize the information per symbol. This optimization results in equal or higher spectrum utilization, and avoids serious and difficult technical problems in discrimination between large numbers of transmitters operating at the same time in the same frequency space and to a common destination.
The negative aspects are that the peak power required is in the same ratio as the reciprocal of the duty cycle. Though the average power is constant for a given speed of information transfer whether the transmission is continuous or burst. While the burst can require circuits which are less efficient because of peak power limitations, this point is much less important for milliwatt power levels.
There is a question of whether the range is greater for the more highly coded case. This point is not yet settled, but it is the opinion of this inventor that the advantage of great coding gain is undone by the liability of noise from simultaneous users.
If the plan must produce high communication capacity, the range will be shortened for this reason before the effects of time dispersion limit range.
The spending of code space for any combination of channelization and data transfer rate is a tradeoff. This invention maximizes data rate for a single channel, and accepts the burdens of fast transition between on and off. It avoids the need for channelization and an assignment protocol to negotiate the channel to be used for each data transfer.